Fpga Implementations of High Throughput Sequential and Fully Pipelined Aes Algorithm*

In this paper, we use FPGA chips to realize the high throughput 128 bits AES cipher processor with new high-speed and hardware sharing functional blocks. The AES functional calculations include four transformation stages, which are the SubBytes, the ShiftRows, the MixColumns and the AddRoundKey. First, the content-addressable memory(CAM) based scheme is used to realize the proposed pipelined high-speed SubBytes block. Second, the new hardware sharing architecture is applied to implement the proposed high-speed MixColumns block. Then the efficient low-cost AddRoundKey architecture is used for real-time key generations. The utilized FPGA tool is Xilinx ISE 7.1 with XST synthesizer. In our proposed sequential AES design, the operational frequency can reach 75.3MHz and the throughput can be up to 0.876Gbits/s. In our full pipelined AES design, the operational frequency can process 222MHz and the throughput can be up to 28.4Gbits/s. Both the proposed sequential and full pipelined AES realizations achieve high throughput requirements and can be suitably used for cryptology applications.